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1
Recent advances in computational optimization : results of the Workshop on Computational Optimization WCO 2016
Springer
Fidanova
,
Stefka
algorithm
solution
optimization
algorithms
parallel
fuzzy
input
jobs
machines
feasible
approach
budget
function
schedule
total
values
graph
search
parameters
partitioning
solutions
initial
computational
systems
analysis
evolutionary
proposed
scheduling
output
step
heuristics
obtained
optimal
tiles
constraints
objective
computation
models
sect
memory
method
partition
criteria
developed
population
vertex
presented
distance
instances
cognitive
Godina:
2018
Jezik:
english
Fajl:
PDF, 5.31 MB
Vaši tagovi:
0
/
0
english, 2018
2
Hardware Prefetch Control for Intel Atom Cores
Intel
prefetch
streamer
uint64_t
core
intel
amp
mlc
requests
atom
cores
prefetcher
prefetches
llc
cache
ddr
demand
prefetchers
msr
001us
nlp
disabled
density
instruc
module
threshold
confidence
respec
configura
prefetching
tracking
0x1a4
trackers
bandwidth
caches
disable
parameters
paterns
throtling
allow
counters
distance
enable
entry
ipp
loads
shared
tuning
aggressive
affects
bits
Godina:
2023
Jezik:
english
Fajl:
PDF, 389 KB
Vaši tagovi:
0
/
5.0
english, 2023
3
Intelligent Memory Systems: Second InternationalWorkshop, IMS 2000 Cambridge, MA, USA, November 12, 2000 Revised Papers
Springer-Verlag Berlin Heidelberg
Junji Ogawa
,
Mark Horowitz (auth.)
,
Frederic T. Chong
,
Christoforos Kozyrakis
,
Mark Oskin (eds.)
memory
cache
chip
dram
architecture
prefetch
prefetching
processor
compiler
latency
node
vector
bandwidth
caches
figure
pim
accesses
systems
content
prefetcher
viram
scima
instruction
benchmark
execution
rate
dynamic
shows
mechanism
benchmarks
addresses
wave
off
pointer
stride
conventional
array
macro
technology
processors
nodes
vls
analysis
operations
accessed
banks
cycle
locality
proceedings
computation
Godina:
2001
Jezik:
english
Fajl:
PDF, 5.62 MB
Vaši tagovi:
0
/
0
english, 2001
4
Intelligent Memory Systems: Second InternationalWorkshop, IMS 2000 Cambridge, MA, USA, November 12, 2000 Revised Papers
Springer-Verlag Berlin Heidelberg
Junji Ogawa
,
Mark Horowitz (auth.)
,
Frederic T. Chong
,
Christoforos Kozyrakis
,
Mark Oskin (eds.)
memory
cache
chip
dram
architecture
prefetch
prefetching
processor
compiler
latency
node
vector
bandwidth
caches
figure
pim
accesses
systems
content
prefetcher
viram
scima
instruction
benchmark
execution
rate
dynamic
shows
mechanism
benchmarks
addresses
wave
off
pointer
stride
conventional
array
macro
technology
processors
nodes
vls
analysis
operations
accessed
banks
cycle
locality
proceedings
computation
Godina:
2001
Jezik:
english
Fajl:
PDF, 2.78 MB
Vaši tagovi:
0
/
0
english, 2001
1
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